1. Field of the Invention
The present invention relates to an apparatus and a method for controlling direct memory access (DMA) in a data processing apparatus that requires high-speed data transfer.
2. Description of the Related Art
In a computer system, it is desirable to perform effective high-capacity data transfer between memories or a memory and an input/output device (I/O device). DMA is a well known method for solving this problem (refer to, for example, Japanese laid-open Patent application No 05-216,808).
An I/O device transfers data to a memory and receives data transferred from the memory. This device includes a memory apparatus and an interface apparatus. DMA has a mechanism in which exclusive hardware called a DMA control circuit controls data transfer on the basis of a command from the central processing unit (CPU), instead of the CPU, itself, controlling the data transfer in a computer system.
The command that is issued to a DMA control circuit from a CPU is called a descriptor. A method such that the DMA control circuit autonomously reads out the descriptor from a memory and refers to the descriptor after the CPU prepares the descriptor on the memory is widely used.
FIG. 1A shows a configuration example of a conventional data processing apparatus provided with a DMA control circuit. The data processing apparatus of FIG. 1A comprises a data transfer control apparatus 101 and I/O devices 102a and 102b. The data transfer control apparatus 101 comprises a CPU 111, a memory 112, a memory controller 113 and an I/O controller 114.
A CPU 111, a memory 112 and an I/O controller 114 are connected to the memory controller 113. The I/O devices 102a and 102b are connected to the I/O controller 114. The number of I/O devices connected to the I/O controller 114 is not restricted to two and generally, one or a plurality of I/O devices is connected.
The memory controller 113 controls data transfer between the CPU 111 and the memory 112 and also between the I/O controller 114 and the memory 112. A DMA control circuit 121 included in the I/O controller 114 performs data transfer between the memory 112 and the I/O device 102 through the memory controller 113. Also, the CPU 111 and the I/O controller 114 receive and transmit control information through the memory controller 113.
FIG. 1B shows a block diagram of the I/O controller 114 of FIG. 1A. The I/O controller 114 of FIG. 1B comprises the DMA control circuit 121, a memory interface (I/F) 122 and an I/O device interface 123.
The DMA control circuit 121 comprises a descriptor fetch circuit 131, a descriptor buffer 132, a state machine circuit 133, a data transfer control circuit 134 and a register 135.
The CPU 111 activates the descriptor fetch circuit 131 and the state machine circuit 133 by writing the activation instructions in the register 135 through the memory interface 122.
The descriptor fetch circuit 131 reads out a descriptor from the memory 112 through the memory interface 122. The descriptor buffer 132 receives the descriptor from the descriptor fetch circuit 131 and stores it. The state machine circuit 133 analyzes the descriptor and instructs the data transfer control circuit 134 about data transfer. Upon receipt of the instruction from the state machine circuit 133, the data transfer control circuit 134 performs data transfer through the memory interface 122 and the I/O device interface 123.
FIG. 1C shows one example of a descriptor. The descriptor of FIG. 1C has a length of 8 bytes*3 words (24 bytes) and it comprises a command, a flag, a transfer byte length, a memory address and an I/O address.
A command is a bit that instructs the direction of data transfer. For example, if a bit is logic ‘0’, it indicates read transfer, that is, data transfer from the I/O device 102 to the memory 112. If a bit is logic ‘1’, it indicates write transfer, that is, data transfer from the memory 112 to the I/O device 102.
A flag is a bit that controls various operations of DMA. For example, such a bit instructs the DMA control circuit 121 to generate an interrupt after the termination of data transfer. A transfer byte length indicates a field for instructing the DMA control circuit 121 about the length (number of bytes) of data to be transferred between the memory 112 and the I/O device 102.
At the time of read transfer, a memory address shows an address on the memory 112 that stores data read out from the I/O device 102. At the time of a write operation, a memory address shows the address on the memory 112 that stores data to be transferred to the I/O device 102. An I/O address shows both a number of the I/O device 102 for reading out data and an address in this device at the time of a read operation while this address indicates both a number of the I/O device 102 for writing data and an address in this device at the time of a write operation.
Then, the following is the explanation for each of DMA write and read operations in reference to the operation sequence of FIG. 1D.
<Write Operation>
    (1) The CPU 111 prepares transfer data in the address designated by a descriptor on the memory 112.    (2) The CPU 111 prepares the descriptor for write transfer in the address predetermined on the memory 112 using the format of FIG. 1C.    (3) The CPU 111 activates the DMA control circuit 121 by writing an activation instruction in the register 135 inside of the DMA control circuit 121.    (4) When the DMA control circuit 121 is activated by the CPU 111, it reads out the descriptor from the predetermined address on the memory 112.    (5) The DMA control circuit 121 analyzes the read-out descriptor and reads out data of the designated transfer byte length from the memory address designated in the descriptor if the command is a write instruction.    (6) Subsequently, the DMA control circuit 121 transfers the data read out from the memory 112 to the I/O device 102 on the basis of the I/O address designated in the descriptor.    (7) When the data transfer terminates, the DMA control circuit 121 transmits an interrupt signal to the CPU 111 in accordance with the instructions of a flag in the descriptor and notifies a data transfer termination.<Read Operation>    (11) The CPU 111 secures a region for transfer data in the address designated by a descriptor on the memory 112.    (12) The CPU 111 prepares the descriptor for read transfer using the format of FIG. 1C in the predetermined address on the memory 112.    (13) The CPU 111 activates the DMA control circuit 121 by writing an activation instruction in the register 135 inside of the DMA control circuit 121.    (14) When the DMA control circuit 121 is activated by the CPU 111, it reads out the descriptor from the predetermined address.    (15) The DMA control circuit 121 analyzes the read-out descriptor and in case of a read instruction, the circuit reads out the data of the designated transfer byte length from the I/O device 102 indicated by the I/O address designated in the descriptor.    (16) Subsequently, the DMA control circuit 121 writes the data read out from the I/O device 102 in the memory address designated by the descriptor.    (17) When the data transfer terminates, the DMA control circuit 121 transmits an interruption signal to the CPU 111 in accordance with the instructions of a flag in the descriptor and notifies a data transfer termination.
As is apparent from the above-mentioned operation sequence, when the CPU 111 prepares a descriptor and activates the DMA control circuit 121, it can perform another processing while data transfer is being performed until a notification is given by the interruption signal. In this way, since the CPU 111 is released from a comparatively simple process such as data transfer and can devote a time to a more complicated process, the performance of the system improves.
There is the following problem in the above-mentioned conventional DMA control method.
The DMA control circuit is effective for reducing the load of a CPU by performing data transfer in place of a CPU and also for enhancing the processing performance of a system thereof. In a conventional DMA control method, however, data transfer is performed after the DMA control circuit reads out the descriptor on a memory prepared by the CPU. Therefore, there is a case such that sufficient performance cannot be obtained in the case where the access•latency (time required for reading out a descriptor) from a DMA control circuit to a memory is large. This problem prominently occurs especially in the case where short data is transferred.
In the case of transferring short data, the transfer time between a DMA control circuit and an I/O device is shorter in comparison with a time required for the transfer of long data. However, a time required for the other control operation is almost identical to a time required for the transfer of long data. Therefore, the ratio of a time required for a control operation other than the data transfer to the whole operation time becomes high in comparison with a time required for the transfer of long data, thereby decreasing the efficiency of the data transfer.